1. Technical Field
The present invention relates to a liquid crystal display device and a method of driving the same.
2. Related Art
Some display devices use cathode-ray tubes (CRTs). Other display devices may be flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays (FED), and electro-luminescence displays (ELDs). Some of these flat panel displays may be driven by an active matrix driving method in which a plurality of pixels arranged in a matrix configuration are driven using a plurality of thin film transistors. Among these active matrix type flat panel displays, liquid crystal display (LCD) devices and electroluminescent display (ELD) devices may have a higher resolution, and increased ability to display colors and moving images as compared to some of the other flat panel display devices.
An LCD device may include two substrates that are spaced apart and face each other with a layer of liquid crystal molecules interposed between the two substrates. The two substrates may include electrodes that face each other. A voltage applied between the electrodes may induce an electric field across the layer of liquid crystal molecules. The alignment of the liquid crystal molecules may be changed based on an intensity of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device may display images by varying the intensity of the electric field across the layer of liquid crystal molecules.
FIG. 1 is a block diagram illustrating an LCD device according to the related art, and FIG. 2 is a circuit diagram illustrating a liquid crystal panel of FIG. 1.
Referring to FIG. 1, the LCD device includes a liquid crystal panel 2 and a driving circuit 26. The driving circuit 26 may include gate and data drivers 20 and 18, a timing controller 12, a gamma reference voltage generator 16, a power supply 14 and an interface 10.
Referring to FIG. 2, the liquid crystal panel 2 includes a plurality of gate lines GL1 to GLn along a first direction and a plurality of data lines DL1 to DLm along a second direction.
The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm cross each other to define a plurality of sub-pixels. Each sub-pixel includes a thin film transistor TFT and a liquid crystal capacitor LC. The liquid crystal capacitor LC includes a pixel electrode connected to the thin film transistor TFT, a common electrode, and a liquid crystal layer between the pixel and common electrodes. Red (R), green (G) and blue (B) sub-pixels forms one pixel.
Referring to FIG. 1, the interface 10 is supplied with red (R), green (G) and blue (B) data and control signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a data clock signal. The RGB data and control signals are supplied from an external system, such as a computer system.
The timing controller 12 is supplied with the control signals from the interface 10 and generates control signals to control the gate and data drivers 20 and 18. The timing controller 12 processes the RGB data and supplies the processed data to the data driver 18. The gate driver 20 is supplied with the control signals from the timing controller 12 to sequentially output gate voltages to the gate lines GL1 to GLn. The gate lines GL1 to GLn are sequentially selected, and the thin film transistors TFT connected to the selected gate line GL1 to GLn are turned on. The data driver 18 is supplied with the RGB data and the control signals from the timing controller 12. The data driver 18 outputs data voltages to the data lines DL1 to DLm when the gate line GL1 to GLn is selected.
The gamma reference voltage generator 16 generates gamma reference voltages which are supplied to the data driver 18. The gamma reference voltages are used to generate the RGB data voltages corresponding to the RGB data. The R, G and B data voltages are inputted to the corresponding R, G and B sub-pixels.
The power supply 14 supplies voltages that operate the components of the LCD device.
Even though not shown in the drawings, the LCD device includes a backlight unit to supply light for the liquid crystal panel 2.
The LCD device is usually supplied with 8-bit RGB data from the external system. Accordingly, the driving circuit, for example, the data driver needs driving ICs capable of processing the 8-bit data. However, the driving ICs cost high.
To reduce the cost, the LCD device uses driving ICs processing the RGB data having a bit number less than eight. To use the driving ICs, a data-processing method to convert the 8-bit data into the data having the lower bit number is required. To do this, a frame rate control (FRC) method is suggested. The timing controller 12 performs the FRC operation.
In detail, the timing controller 12 reconstructs frame data such that the LCD device including the driving ICs which process (n−m)-bit data displays images using (n−m) bits among n bits of an n-bit RGB input data.
The m indicates a bit number of lower bits of the input data. The timing controller 12 converts the n-bit input data into an (n−m)-bit data such that among consecutive 2m frames, a number of frames where the converted data has a gray level A represented by the upper (n−m) bits of the input data and a number of frames where the converted data has a next higher gray level (A+1) are adjusted according to the lower m bits of the input data.
Furthermore, the timing controller 12 converts the n-bit input data into a predetermined number of (n−m)-bit data, respectively, assigned to a predetermined number of pixels in a pixel block such that a total number of pixels displaying the gray level A and the total number of pixels displaying the gray level (A+1) for each of 2m frames are adjusted according to the lower m bits of the input data.
Because human eyes recognize spatio-temporal average of the gray level of the (n−m)-bit data, the image appears the same as that displayed by the n-bit data. Accordingly, 2m gray levels between the gray levels A and (A+1) can be additionally displayed.
FIG. 3 is a block diagram illustrating a timing controller of an LCD device according to the related art.
Referring to FIG. 3, a timing controller 12 includes an FRC portion 13 to perform an FRC operation. The FRC portion 13 converts R, G and B input data into R′, G′ and B′ data. For example, the input data is 9-bit data and the converted data is 6-bit data. The external system usually supplies 8-bit RGB data to the LCD device. The timing controller 12 expands the 8-bit RGB data into a 9-bit RGB data through a process such as adding a lowermost bit having a value of 0 to the 8-bit RGB data. The expanded 9-bit data is inputted to the FRC conversion 13 as the input data.
According to values of lower 3 bits of the 9-bit input data, upper 6 bits of the 9-bit RGB input data are processed to generate the 6-bit RGB data. For example, the FRC conversion 13 converts the 9-bit RGB input data into the 6-bit RGB data, respectively, assigned to pixels, each of which has R, G and B sub-pixels, of a pixel block using a look-up table (LUT) according to the lower 3 bits of the 9-bit input data. In other words, the 9-bit input data is converted into the 6-bit data, respectively, assigned to the pixels of the pixel block for 2m frames according to the lower 3 bits.
Accordingly, an FRC pattern of the converted data generated by the FRC portion 13 depends on the lower 3 bits of the input data.
FIG. 4 is a view illustrating FRC patterns of R, G and B data generated through an FRC portion of an LCD device according to the related art. In FIG. 4, a pixel block includes eight pixels in a 2×4 (two rows by four columns) matrix. Each pixel includes R, G and B sub-pixels. For convenience of explanation, the R, G and B sub-pixels of pixels in a matrix form are separately described in FIG. 4. In other words, a top portion of FIG. 4 describes the R sub-pixels of the pixels, a center portion of FIG. 4 describes the G sub-pixels of the pixels, and a bottom portion of FIG. 4 describes the B sub-pixels of the pixels. Further, for convenience of explanation, FIG. 4 describes the FRC patterns for former four frames Sth to (S+3)th frames among consecutive eight frames.
Referring to FIG. 4, converted 6-bit R, G and B data (R′, G′ and B′ of FIG. 3) through the FRC portion (13 of FIG. 3) are written to the corresponding R, G and B sub-pixels during Sth to (S+3)th frames. In other words, data voltages corresponding to the converted R, G and B data are applied to the corresponding R, G and B sub-pixels. The R, G and B sub-pixels each alternately have a positive or negative polarity per frame according to an inversion operation. Hatched sub-pixels each have a gray level A represented by upper 6 bits of an 9-bit input data, and non-hatched sub-pixel each have a next higher gray level (A+1) to the gray level A represented by the upper 6 bits of the 9-bit input data.
Because the R, G and B data are commonly converted through the related art FRC portion, the converted R, G and B data have the same FRC pattern. For example, in each pixel block, arrangement of the hatched R, G and B sub-pixels and the non-hatched R, G and B sub-pixels are the same for each frame. Accordingly, a case may occur where the higher gray level R, G and B data are concentrated on some specific pixels of the pixel blocks. This causes pattern such as flowing line pattern 30 and lattice pattern 40 in some regions as described in FIG. 5 or flicker, and thus display quality is degraded.